Can personality traits be measured analyzing written language? a meta-analytic study on computational methods

In the last two decades, empirical evidence has shown that personality traits could be related to the characteristics of written language. This study describes a meta-analysis that synthesizes 23 independent estimates of the correlations between the Big Five major personality traits, and some computationally obtained indicators from written language. The results show significant combined estimates of the correlations, albeit small to moderate according to Cohen's conventions to interpret effect sizes, for the five traits (between r = 0.26 for agreeableness and neuroticism, and 0.30 for openness). These estimates are moderated by the type of information in the texts, the use of prediction mechanisms, and the source of publication of the primary studies. Generally, the same effective moderators operate for the five traits. It is concluded that written language analyzed through computational methods could be used to extract relevant information of personality. But further research is still needed to consider it as predictive or explanatory tool for individual difference

HLStool: Una herramienta de Síntesis de Alto Nivel para el aprendizaje del estudiante en asignaturas de ATC

La utilización de herramientas de Síntesis de Alto Nivel (SAN) es una práctica habitual en las empresas dedicadas al diseño de circuitos. El principal beneficio de estas herramientas se basa en la reducción del “tiempo de lanzamiento al mercado”, ya que permiten evaluar múltiples soluciones en un tiempo reducido. En esta contribución, se propone el uso de una herramienta de síntesis altamente visual y amigable que contenga los algoritmos clásicos para enseñar al alumno las técnicas básicas de SAN, y adicionalmente familiarizarle con el método de trabajo de las compañías de diseño de circuitos. Con esta contribución se propone ofrecer una formación más completa a los futuros graduados que cursen asignaturas del área de la Arquitectura y Tecnología de Computadores.The use of High-Level Synthesis (HLS) tools is a common practice in circuit design companies. The main benefit of these tools consists of diminishing time to market, as they provide multiple solutions to explore in a reduced amount of time. In this paper we propose the use of a highly visual synthesis tool, which implements the classic algorithms to teach students the basic HLS concepts and to get them closer to the companies’ methodology. In this way, Computer Architecture and Technology related subjects will offer a more complete programme to the future graduates.Universidad de Granada: Departamento de Arquitectura y Tecnología de Computadores; Vicerrectorado para la Garantía de la Calidad

Una Orquesta Sinfónica como Ejemplo de Aplicación de un Sistema Empotrado Distribuido

El presente artículo trata sobre el diseño e implementación de una orquesta sinfónica distribuida haciendo uso del paquete de Lego Mindstorms, como proyecto final enmarcado dentro de la asignatura Sistemas Empotrados Distribuidos. En esta contribución se aplican los conocimientos obtenidos en dicha asignatura, en la que se fomenta la aplicación de los mismos para la realización de proyectos novedosos. En este artículo se describen el diseño, las diversas tecnologías evaluadas y la implementación final.This paper discusses the design and implementation of a distributed symphony orchestra using the Lego Mindstorms package, as a final project belonging to the Distributed Embedded Systems subject. In this contribution, the knowledge achieved during the subject is applied. It must be noted that the application of the studied contents to create novel projects is greatly encouraged. In this paper the design, the evaluation of several technologies, as well as the final implementation, are presented.Universidad de Granada: Departamento de Arquitectura y Tecnología de Computadores; Vicerrectorado para la Garantía de la Calidad

Experiencia interuniversitaria de docencia en un curso clásico de sistemas digitales dentro del EEES

Reflexionamos respecto a los cursos clásicos de sistemas digitales impartidos dentro del Espacio Europeo de Educación Superior (EEES), contextualizamos dos casos prácticos de estudio: La Universidad Complutense de Madrid y la Universidad de Granada. Finalizamos el presente trabajo con los datos de una encuesta docente diseñada al efecto que nos permita correlacionar la opinión del estudiante con la distribución temática y organizativa de la asignatura. Creemos que esta primera experiencia puede ser utilidad para otros Centros de Educación Superior que aborden la misma temática.Departamento de Arquitectura y Tecnología de Computadores (Universidad de Granada

Customized Nios II multi-cycle instructions to accelerate block-matching techniques

This study focuses on accelerating the optimization of motion estimation algorithms, which are widely used in video coding standards, by using both the paradigm based on Altera Custom Instructions as well as the efficient combination of SDRAM and On-Chip memory of Nios II processor. Firstly, a complete code profiling is carried out before the optimization in order to detect time leaking affecting the motion compensation algorithms. Then, a multi-cycle Custom Instruction which will be added to the specific embedded design is implemented. The approach deployed is based on optimizing SOC performance by using an efficient combination of On-Chip memory and SDRAM with regards to the reset vector, exception vector, stack, heap, read/write data (.rwdata), read only data (.rodata), and program text (.text) in the design. Furthermore, this approach aims to enhance the said algorithms by incorporating Custom Instructions in the Nios II ISA. Finally, the efficient combination of both methods is then developed to build the final embedded system. The present contribution thus facilitates motion coding for low-cost Soft-Core microprocessors, particularly the RISC architecture of Nios II implemented in FPGA. It enables us to construct an SOC which processes 50×50 @ 180 fps

Smith-Waterman Protein Search with OpenCL on an FPGA

The well-known Smith-Waterman (SW) algorithm is a high-sensitivity method for local alignments. Unfortunately, SW is expensive in terms of both execution time and memory usage, which makes it impractical in many scenarios. Previous research has shown that massively parallel architectures such as GPUs and FPGAs are able to mitigate the computational problems and achieve impressive speedups. In this paper we explore SW acceleration on an FPGA with OpenCL. We efficiently exploit data and thread-level parallelism on an Altera Stratix V FPGA, obtaining up to 39 GCUPS with less than 25 watt of power consumption.Facultad de Informátic

Smith-Waterman Protein Search with OpenCL on an FPGA

The well-known Smith-Waterman (SW) algorithm is a high-sensitivity method for local alignments. Unfortunately, SW is expensive in terms of both execution time and memory usage, which makes it impractical in many scenarios. Previous research has shown that massively parallel architectures such as GPUs and FPGAs are able to mitigate the computational problems and achieve impressive speedups. In this paper we explore SW acceleration on an FPGA with OpenCL. We efficiently exploit data and thread-level parallelism on an Altera Stratix V FPGA, obtaining up to 39 GCUPS with less than 25 watt of power consumption.Facultad de Informátic

An energy‐aware performance analysis of SWIMM: Smith–Waterman implementation on Intel's Multicore and Manycore architectures

Alignment is essential in many areas such as biological, chemical and criminal forensics. The well‐known Smith–Waterman (SW) algorithm is able to retrieve the optimal local alignment with quadratic time and space complexity. There are several implementations that take advantage of computing parallelization, such as manycores, FPGAs or GPUs, in order to reduce the alignment effort. In this research, we adapt, develop and tune the SW algorithm named SWIMM on a heterogeneous platform based on Intel's Xeon and Xeon Phi coprocessor. SWIMM is a free tool available in a public git repository https://github.com/enzorucci/SWIMM. We efficiently exploit data and thread‐level parallelism, reaching up to 380 GCUPS on heterogeneous architecture, 350 GCUPS for the isolated Xeon and 50 GCUPS on Xeon Phi. Despite the heterogeneous implementation obtaining the best performance, it is also the most energy‐demanding. In fact, we also present a trade‐off analysis between performance and power consumption. The greenest configuration is based on an isolated multicore system that exploits AVX2 instruction set architecture reaching 1.5 GCUPS/Watts.Facultad de Informátic

OSWALD: OpenCL Smith–Waterman on Altera’s FPGA for Large Protein Databases

The well-known Smith–Waterman algorithm is a high-sensitivity method for local sequence alignment. Unfortunately, the Smith–Waterman algorithm has quadratic time complexity, which makes it computationally demanding for large protein databases. In this paper, we present OSWALD, a portable, fully functional and general implementation to accelerate Smith–Waterman database searches in heterogeneous platforms based on Altera’s FPGA. OSWALD exploits OpenMP multithreading and SIMD computing through SSE and AVX2 extensions on the host while taking advantage of pipeline and vectorial parallelism by way of OpenCL on the FPGAs. Performance evaluations on two different heterogeneous architectures with real amino acid datasets show that OSWALD is competitive in comparison with other top-performing Smith–Waterman implementations, attaining up to 442 GCUPS peak with the best GCUPS/watts ratio.First published June 30, 2016. Article available in: Vol. 32, Issue 3, 2018.Facultad de Informátic

Smith-Waterman algorithm on heterogeneous systems: A case study

The well-known Smith-Waterman (SW) algorithm is a high-sensitivity method for local alignments. However, SW is expensive in terms of both execution time and memory usage, which makes it impractical in many applications. Some heuristics are possible but at the expense of losing sensitivity. Fortunately, previous research have shown that new computing platforms such as GPUs and FPGAs are able to accelerate SW and achieve impressive speedups. In this paper we have explored SW acceleration on a heterogeneous platform equipped with an Intel Xeon Phi coprocessor. Our evaluation, using the well-known Swiss-Prot database as a benchmark, has shown that a hybrid CPU-Phi heterogeneous system is able to achieve competitive performance (62.6 GCUPS), even with moderate low-level optimisations.Facultad de Informátic